(1) Field of the Invention
The invention generally relates to a semiconductor memory and more particularly, to a circuit and method to track the current variations in SRAM memory cell devices fabricated on an integrated circuit (IC).
(2) Description of Prior Art
In a standard static random access memory (SRAM), memory cells are arranged in an array of rows and columns. The memory cells each typically comprise four or six transistors as shown in FIGS. 1a and 1b, respectively. Refer now to the four-transistor memory cell of FIG. 1a. A latch is formed with T1, T2, R1 and R2. If the cell is storing a memory value such that node A is high (pulled up through R1), the gate of NMOS transistor T2 is high, thereby turning on T2. This pulls node B and the gate of NMOS transistor T1 low thereby turning T1 off and holding node A high. Conversely, if the cell is storing the opposite value, node A would be low and node B would be high. The six-transistor cell of FIG. 1b functions in essentially the same way except that PMOS transistors T5 and T6 replace the pull-up resistors R1 and R2.
Each memory cell is connected to one of a plurality of word lines (WL) and to one of a plurality of bit lines (BL) and their inverses (BLB). Memory writing is accomplished by placing a high level (1) on the addressed word line and the desired logic level on the bit lines (BL and BLB) and latching the desired value through pass NMOS transistors T3 and T4. Memory reading is accomplished by placing a high level (1) on the addressed word line and detecting currents in a sense amplifier (not shown) through pass NMOS transistors T3 and T4.
In larger SRAM devices, the memory cell array is divided into sections because use of a large single array results in degradation of the device speed performance due to the long word lines which add additional resistance in word, bit and supply lines. This compounds the switching speed problem resulting from increased capacitive loading driven by the increased memory capacity.
Another problem inherent to large SRAM devices is the wide distribution of the memory cell current characteristics within the device. These variations can result in misinterpretation of the data stored in the memory cell by the sense amplifier. The current variations are a result of process variations, cell placement within the device and the aggressive design rules necessary to reduce the size of the memory cells.
Power strapping is a method where multiple path VDD and VSS (ground) signals are strapped to each memory cell to aid in the reduction of sagging and bumping of VDD and VSS potentials during the simultaneous addressing of multiple memory cells or unbalanced supply lines. In cases where the strap contacts are misaligned, the straps may not be completely effective. U.S. Pat. No. 5,831,315 to Kengeri et al. teaches a method whereby VSS straps are created with some alignment tolerance. However, in large capacity advanced SRAM memory design, VSS power strapping for each cell is limited. The voltage bump on the source side of the pull-down NMOS transistors (T1 and T2) will degrade the cell current during the bump transient. In some bit cell designs, the voltage bump on the low (0) side of the latch may partially turn on the pull-down NMOS (T1 or T2) on the high (1) side of the latch. This voltage dip on the high side may reduce still further the current on the low side.
One other effect which may degrade the cell current is ground bouncing phase-shift (GBPS). The VSS line is grounded and electrically connected to the sources of the pull down NMOS transistors (T1 and T2). The circuit is formed in a p-substrate electrically connected to ground using substrate contacts distributed throughout the integrated circuit. Noise from switching on the ground supply line will appear first on the substrate and then, due to distributed resistance and capacitance, appear on the VSS line. This results in a voltage difference between the sources of the pull down NMOS transistors (T1 and T2) and the p-substrate. This difference in potential will cause the current characteristics of the memory cells to change whenever the substrate potential falls below the VSS line potential.
Because of process variations across the integrated circuit, the wide variation in cell current distribution seen during switching is common in larger capacity SRAM devices. To overcome the problems caused by process variations in sensing the cell current, additional margin is typically added to the access time. U.S. Pat. No. 6,111,813 to Huang teaches a method whereby the sense amplifier in a synchronous RAM is enabled by detection of a global word line and sub-word line signals rather than after a fixed margin after a clock pulse. Using sub-word lines, Huang reduces the overall capacitive load. The use of these sub-word line signals to enable the sense amplifier reduces the amount of necessary margin added to the access time. U.S. Pat. No. 6,072,732 to McClure describes a method whereby a reset is applied after a fixed delay following activation of a word line in a memory device. This minimizes access time and prevents simultaneous writing of sequentially addressed word lines. The present invention minimizes the differences between tracking cell and addressed memory cell thereby eliminating the necessity of margin being added to the access time.
A principal object of the present invention is to provide a method that reduces access time in an SRAM device.
A second object of the present invention is to provide a method of tracking bit line current in a memory cell.
Another object of the present invention is to provide a circuit for tracking bit line current in a memory cell.
A further object of the present invention is to provide a circuit for bit line tracking capable of tracking a wider distribution of memory cell current.
A still further object of the present invention is to provide a circuit for bit line tracking capable of tracking cell current under conditions due to ground bumping on the power lines.
A still further object of the present invention is to provide a circuit for bit line tracking capable of tracking cell current under conditions due to voltage sagging on the high side of the memory cell latch.
A still further object of the present invention is to provide circuit for bit line tracking capable of tracking cell current under conditions due variations in strap cell alignment.
A still further object of the present invention is to provide a method that eliminates the body effect caused by ground bounce phase shifting.
A still further object of the present invention is to provide a strap circuit that eliminates the body effect caused by ground bounce phase shifting.
These objects are achieved using a method for tracking memory cell currents using a tracking memory cell circuit whereby the challenges resulting from current degradation and process variations are eliminated. A special strap cell is provided to eliminate ground bounce phase shifting. The tracking and strap cells along with the tracking scheme allow for better tracking of current within the array without the necessity of adding timing margin. The tracking memory cell circuit is a modified version of the memory cell used in the memory array. The tracking memory cell current provides a reference current for the sense amplifier that is compared against the addressed memory cell. Tracking cells are placed in the center of the memory array making them nearer to the active memory cells. They better mirror the physical and electrical characteristics of the active memory cells over previous methods. The strap cell makes contact between the VSS metal line and a lightly doped n-type region within the p-substrate. This forms a low Vth diode with a turn-on voltage between about 0 and 0.2 volts between the substrate and VSS. This strapping of VSS to the substrate reduces the effect of ground bounce phase shifting.